Future improvements in metal-oxide-semiconductor field effect transistors (MOSFETs) performance will require high mobility (high-μ) semiconductor channels. The integration of novel materials with higher carrier mobility, to increase drive current capability, is a real challenge to overcome silicon-based CMOS. One solution is to use a germanium-based channel for pMOS combined with an III-V-based channel for nMOS. The main issues of such devices consist in obtaining low leakage current, low interface state density and high carrier mobility in the channel.
Therefore, passivation of the interface between gate oxide and Ge/III-V materials will require innovations to reach high device performances and EOT scaling. For this reason, a great technological effort is required to produce systems that yield the desired quality in terms of material purity, uniformity and interface control.
Molecular Beam Epitaxy (MBE) has been shown to be an attractive technique to fabricate such devices, due to its potential to control at an atomic scale the in-situ deposition of the high-κ oxides and also the layer at the high-μ substrates interface.
Gallium arsenide (GaAs), with its intrinsically superior electron mobility, has been considered as a good candidate for sub-15 nm node n-MOS. The high interface states density Dit at the oxide/GaAs interface is the main origin of Fermi level pinning which disturbs the basic MOSFET-operation.
Several passivation techniques have been attempted to prevent Fermi level pinning: chalcogenide or hydrogen surface treatments as described e.g. by Callegari et al. in Appl. Phys. Lett. 93, 183504 (2008); molecular beam epitaxy-grown Ga2O3(Gd2O3) oxide as described e.g. by Hong et al. in Science 283, 1897 (1999); or interfacial passivation layers such as amorphous Si or amorphous Ge as described e.g. by Kim et al. in Appl. Phys. Lett 92, 032907 (2008). Although considerable improvements have been realized in Dit reduction, further developments are required to obtain high performance MOS devices.
U.S. Pat. No. 6,159,834 discloses growing a GaGdOx oxide epitaxially on top of an III-V substrate. The GaGdOx oxide stabilizes the surface reconstruction of the III-V substrate, which minimizes the interface stress and leads to an unpinned Fermi level. However, the method limits the integration options to the use of the specific GaGdOx which can show significant leakage.
An alternative method described by De Souza et al. in Appl. Phys. Letters 92 153508 (2008) consists of depositing an amorphous layer of silicon on top of an III-V substrate (GaAs). However, this approach does not control the stress induced in the substrate and the electron-counting that governs the Fermi level pinning at the interface.
Therefore it is desirable to find a method that will effectively passivate an III-V substrate without presenting the drawbacks as cited above and which will lead to a device with improved performance.